Standby Voltage Scaling for Reduced Power
نویسندگان
چکیده
Lowering VDD during standby mode reduces power by decreasing both voltage and current. Measurements of a 0.13 m testchip show that reducing VDD to near the point where state is lost gives the best power savings. We propose closed-loop voltage scaling that uses “canary” flip-flops for achieving these savings. This approach provides over 2X higher savings than optimal open-loop approaches without loss of state.
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